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SMM764 preliminary information 1 (see last page) ? summit microelectronics, inc. 2004 ? 1717 fox drive ? san jose ca 95131 ? phone 408 436-9890 ? fax 408 436-9897 the summit web site can be accessed by ?ri ght? or ?left? mouse clicking on the link: http://www.summitmicro.com/ 2098 1.1 6/29/2005 1 four-channel active dc output controller, monito r, marginer and sequencer with sequence-link ? ? extremely accurate (0.2%) output voltages using active dc output control (adoc?) ? sequence-link? provides sequencing of up to 46 channels ? adoc automatically adjusts supply output voltage level under all dc load conditions ? monitors, controls and margins up to 4 supplies from 0.3v to 5.5v ? programmable power-on/-off sequencing ? operates from any intermediate bus supply from 6v to 14v and from 2.7v to 5.5v ? monitors 12v input vdd and temperature sensor ? wide margin/adoc range from 0.3v to vdd ? monitors two general-purpose 10-bit adc inputs ? i 2 c 2-wire serial bus for programming configuration and monitoring status, including 10-bit adc conversion results ? 2 programmable under voltage (uv) and over voltage (ov) threshold limits for each of 9 monitored inputs ? 2k-bit general purpose nonvolatile memory applications ? monitor/control distributed and pol supplies ? multi-voltage processors, dsps, asicss used in telecom, compactpci or server systems the SMM764 is an active dc output power supply controller (adoc tm ) that monitors, margins, and cascade sequences. the adoc feature is unique and maintains extremely accurate settings of system supply voltages to within 0.2% under full load. the SMM764 actively controls up to 4 dc/dc converters and can be linked with up to 7 other sequence-link? devices to accommodate sequencing of up to 46 channels. control of t he dc-dc converters is accomplished through the use of a trim or regulator vadj/fb pin to adjust the out put voltage. for system test, the part also controls margining of the supplies using i 2 c commands. it can margin supplies with either positive or negative control within a range of 0.3v to vdd, depending on the specified range of the converter. the SMM764 also intelligently sequences or cascades the power supplies on and off in any order using enable outputs with programmable polarity. it can operate off any intermediate bus supply ranging from 6v to 14v or from 5.5v to as low as 2.7v. the part monitors 4 power supply channels as well as vdd, 12v input, two general-purpose analog inputs and an internal temperature sensor using a 10-bit adc. the 10-bit adc can measure the value on any one of the monitor channels and output the data via the i 2 c bus. a host system can communicate with the SMM764 status register, margining and utilize 2k-bits of nonvolatile memory. simplified applications drawing trim b pup b vm b trim_cap b cap b trim a pup a vm a trim_cap a cap a SMM764 p/ asic vdd rst# healthy mr# 3.3vin (+2.7v to +5.5v range) reset# ready healthy 12vin 12vin (+6v to +14v range) external or internal temp sensor ain1 2.5vin 1.2vin 12v sda scl i 2 c bus 3.3v a2 vref vin trim vout dc/dc converter a on/off vin trim vout dc/dc converter b on/off external or internal reference environmental sensor ain2 dc/dc converter c, dc/dc converter d, 2 of 4 dc-dc converters shown seq_link to additional sequence- link devices figure 1 ? applications schematic using the SMM764 controller to actively control the output levels of up to 4 dc/dc converters while also providing powe r-on/off, cascade sequencing and output margining. note: this is an applications example only. some pins, components and values are not shown. introduction features & applications
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 2 table of contents general descrip tion?????????...? ????3 internal functional block diagram??..? ?????4 pin descriptions????????????? ??..5-6 package and pin configuration??????? ??..7 absolute maximum ratings??????? ????.8 recommended operating conditions??? ?..??..8 dc operating characteristics???????.. ?..8-10 ac operating charac teristics??????...? ??.10 i 2 c 2-wire serial interface ac operating characteristics-100/400khz??????? ????11 timing diagrams????????? ?????11-12 device operation power supply?????????????.???.?? ?.14 modes of operat ion?????????...?? ??.14 active dc output control????????? ?.14-15 power-on cascade sequencing?.???? ??.?.15 ongoing operations-monitoring mode??? ?...?..16 temperature sensor accuracy???????? ?..16 margining????????????????? ?..17 power-off cascade sequencing????? ??.?..17 force-shutdown?.????????????? ?.17 linked operation ???????????..?...? ?18 restart?..????????????????.? ?18 i 2 c power-off control?????????...?? ?..18 recommended use of the power on pin??? ?.19 applications schematic??????????? ?..20 development hardware & software???? ?...?..21 i 2 c programming information serial interface.?????????????? ..?..22 write????????? ?????...?.?? ??..22 read?.????????????????? ??.22 write protection?.?????????.???? ?.23 configuration registers?..?????????? ?23 general-purpose memory?.????????? ?.23 command and status registers?????? ??...23 adc conversions?.??????????.??. ?.23 graphical user interface (gui)????????? ..23 write protection regi ster write?????...?? ?..24 configuration regist er read/write???...? ?..24-25 general-purpose memory read/write??..?? ?..26 command and status register read/write?? ?...27 adc conversion read?.????????? ?.?.27 default configuration register settings???. ??..28 package????????????????..? ?..29 part marking ??????????????...? ?..30 ordering information?..?????????.? ??30 terminology and definitions????????? ?..31 legal notice???????????????? ?..32
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 3 the SMM764 is a highly integrated and accurate power supply controller, monitor, and sequencer. each device has the ability to autom atically control, monitor and cascade sequence up to 4 power supplies. in addition, the SMM764 includes sequence-link ? a feature that allows for the seamless integration of other sequence-link devices to accommodate sequencing of up to 46 channels. the SMM764 can monitor the vdd input, the 12v input, two general- purpose analog inputs, and the internal temperature sensor. the SMM764 has four operating modes: power-on sequencing modes, monitor mode, supply margining mode using active dc output control (adoc tm ), and power-off sequencing mode. power-on sequencing is initiated by the rising edge of the pwr_on pin. during power-on sequencing the SMM764 will sequence the power supply channels on, in any order, by activating the pup outputs and monitoring the respective converter voltages to ensure cascading of the supplies. cascade sequencing is the ability to hold off the next sequenced supply until the first supply reaches a programmed threshold. a programmable sequence termination timer can be set to disable all channels if the power-on sequence stalls. once all supplies have sequenced on and the voltages are above the uv settings, the adoc, if enabled, will bring the supply voltages to their nominal settings. during this mode, the healthy output will remain inactive and the rst# output will remain active. once the power-on sequencing mode is complete, the SMM764 enters monitor mode. in the monitor mode, the SMM764 starts the adoc control of the supplies and adjusts the output voltage to the programmed setting under all load conditions, especially useful for supplies without sense lines. typical converters have 2% accuracy ratings for their output voltage; the adoc feature of the SMM764 increases the accuracy to 0.2% (using a 0.1% external voltage reference). the part also enables the triggering of outputs by monitored fault conditions. the 10-bit adc cycles through all 9 channels every 2ms and checks the conversions against the programmed threshold limits. the results can be used to trigger rst#, healthy and fault# outputs as well as to initiate a fault-triggered power-off or force-shutdown operation. while the SMM764 is in its monitoring mode, an i 2 c command to margin the supply voltages can bring the part into margining mode. in margining mode the SMM764 can margin 4 supply voltages in any combination of nominal, high and low voltage settings using the adoc feature, all to within 0.2% using a 0.1% external reference. the margin high and low voltage settings can range from 0.3v to vdd around the converters? nominal output voltage setting depending on the specified margin range of the dc- dc converter. during this mode the healthy output is always active and the rst# output is always inactive regardless of the voltage threshold limit settings and triggers. furthermore, the triggers for power-off and force-shutdown are temporarily disabled. the power-off sequencing mode can only be entered while the SMM764 is in the monitoring mode. it can be initiated by either bringing the pwr_on pin low, through i 2 c control, or triggered by a channel exceeding its programmed thresholds. once power- off is initiated, it will di sable the adoc function and sequence the pup outputs off in the reverse order as power-on sequencing. to ensure cascading of the supplies during power-off sequencing all supplies will be monitored as they tu rn off. the sequence termination timer can be programmed to immediately disable all channels if the power-off sequencing stalls via a force-shutdown operation. 1 2.5v 1.8v 1.5v vdd (+2.7v to +5.5v) or 12vin ( +8v to +15v) 2 3 4 sequence position 1.2v figure 2 ? example power supply sequencing and system start-up initialization using the SMM764. cascade sequencing ensures that all supplies in the previous sequence position are valid before the next channel is released. using the SMM764 any order of supply sequencing can be applied. general description
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 4 ain 2 10-bit adc ain 1 vm a active dc output control (adoc tm ) cap a vm d cap d trim a trim_cap a trim d trim_cap d vref filt_cap 12vin vdd cascade sequence control fs# pwr_on 3.6v or 5.5v regulator power supply arbitrator temperature sensor vdd_cap output control mr# rst# healthy fault# memory, limit and status registers i 2 c interface sda scl a2 gnd uvlo control pup a seq_link pup b pup c pup d figure 3 ? SMM764 internal functional block diagram. internal functional block diagram
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 5 pin descriptions pin number pin type pin name pin description 1 data sda sda (serial data) is an open drain bi-directional pin used as the i 2 c data line. 2 clk scl scl (serial clock) is an open drain input pin used as the i 2 c clock line. 3 in a2 the a2 (address bit 2) pin is biased either to vdd_cap or gnd. when communicating with the SMM764 over the 2-wire i 2 c bus, a2 provides a mechanism for assigning a unique bus address. 4 in mr# mr# (manual reset) is an active low input. when asserted the rst# output will become active. when de-asserted the rst# output will go inactive immediately after a reset timeout period (t rto ) if there are no rst# trigger sources active. this timeout period makes it suitable to use as a pushbutton for manual reset purposes. 5 i/o pwr_on pwr_on (power on) is an open drain bi-directional pin. on the rising edge of pwr_on the part will sequence the supplies on, during the falling edge the part will sequence the supplies off. this pin must be tied high through an external pull-up resistor. note: the SMM764 does not monitor for faults during power-on/off sequencing. 6 i/o fs# fs# (force shutdown) is an open drain ac tive low bi-directional pin. fs# is used to immediately turn off all converter enable signals (pup outputs) when a fault is detected. whenever fs# is asserted pwr_on will automatically be pulled low as well. this pin must be tied high through an external pull-up resistor. 7 out fault# the fault# pin is an active low open drain output. active when a programmed fault condition exists on ain1, ain2, or the internal temperature sensor. when used, fault# should be pulled high through an external pull- up resister. 8 out healthy healthy is an active high open drain output. active when all programmed power supply inputs and monitored input s are within ov and uv limits and adoc has begun. when used, healthy should be pulled high through an external pull-up resistor. 9 out rst# rst# (reset) is an active low open drain output pin. active when a programmed fault condition exists on an y power supply inputs or monitored inputs, when mr# is active, or when adoc is not ready. rst# has a programmable timeout period with options for 0.64ms, 25ms, 100ms and 200ms. when used, rst# should be pulled high through an external pull-up resistor. 10 in ain1 ain1 (analog input 1) is a general-purpose monitored analog input. 11 in ain2 ain2 (analog input 2) is a general-purpose monitored analog input. 12,19, 24 gnd gnd ground.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 6 pin number pin type pin name pin description 13 i/o seq_link seq_link (sequence-link?) is an open drain bi-directional pin. this pin should be attached to other sequence-link devices, during linked operation. seq_link must be pulled high through an external pull-up resistor when multiple sequence-link devices are used. when the SMM764 is not used with another sequence-link device, seq _link should be tied directly to ground. 14 i/o vref vref (voltage reference) is a bi-directional analog pin. vref is used for active dc output control and margining. vref can be programmed to output the internal 1.25v reference, or accept an external reference. vref is also used as a reference for the adc. 15 cap filt_cap filt_cap (filter capacitor) is an external capacitor input used to filter vm x inputs. 16,17, 18,20, 21,22, 23,25 nc no connect leave open, do not connect. these pins must be left floating. 41,36, 31,26 in vm x vm x (voltage monitor) pins are analog inputs. these pins are normally attached to the positive converter sense line, vm a through vm d. 42,37, 32,27 cap cap x external capacitor input used to filter the vm x inputs to the 10-bit adc, cap a through cap d . this provides an rc filter where r = 25k ? .. 43,38, 33,28 out pup x pup x (power up permitted) pins are programmable active high/low open drain converter enable output, pup a through pup d. 44,39, 34,29 out trim x output voltage used to control th e output of dc/dc converters, trim a through trim d. 45,40, 35,30 cap trim_cap x trim_cap x is an analog output pin used to control the output of dc/dc converters. if the adoc/margining functi onality is not used on a channel the associated trim_cap x pin should be l eft floating. there are 4 trim_cap x pins, trim_cap a through trim_cap d . 46 pwr vdd power supply of the part 47 pwr 12vin 12vin (12 volt input) is a power supply input internally regulated to either 3.6v or 5.5v. 48 cap vdd_cap vdd_cap ( vdd capacitor) is an external capacitor input used to filter the internal supply. pin descriptions ( cont. )
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 7 package and pin configuration 48 lead tqfp top view 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 sda scl a2 mr# pwr_on fs# fault# healthy rst# ain1 ain2 gnd seq_link vref filt_cap nc nc nc gnd nc nc nc nc gnd vmb trim_capc trimc pupc capc vmc trim_capd trimd pupd capd vmd nc vdd_cap 12vin vdd trim_capa trima pupa capa vma trim_capb trimb pupb capb
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 8 temperature un der bias....................... -55 c to 125 c storage temper ature............................ -65 c to 150 c terminal voltage with respect to gnd: vdd supply voltage ......................... -0.3v to 6.0v 12vin supply voltage ..................... -0.3v to 15.0v pup a , through pup f ....................... -0.3v to 15.0v all others ................................ -0.3v to v dd + 0.7v output short circ uit current ............................... 100ma lead solder temper ature ( 10 s).......................... 300 c junction temper ature .......................................... 150c esd rating per jedec ....................................... 2000v latch-up testi ng per je dec............................. 100ma note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stre ss ratings only and functional operation of the device at these or any other conditions outs ide those listed in the operational sections of the specificati on is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended. temperature range (industrial)...........?40 c to +85 c (commercial) ..............0 c to +70 c vdd supply voltage .................................. 2.7v to 5.5v 12vin supply voltage 1 ............................ 6.0v to 14.0v vin ............................................................ gnd to vdd vout ...................................................... gn d to 14.0v package thermal resistance ( ja ) 48 lead tqfp ................................................80 o c/w moisture classification level 1 (msl 1) per j-std- 020 reliability characteristics data retentio n .............................................. 100 years endurance ..............................................100,000 cycles dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit vdd supply voltage 2.7 5.5 v internally regulated to 5.5v 10 14 v 12vin supply voltage internally regulated to 3.6v 6 14 v i dd power supply current from vdd all trim pins floating, 12vin floating 3 5 ma i 12vin power supply current from 12vin all trim pins floating, vdd floating 3 5 ma trim characteristics trim sourcing maximum current 1.5 ma i trim trim output current through 100 ? to 1.0v trim sinking maximum current 1.5 ma v trim margin and adoc range depends on trim range of dc-dc converter vref/4 vdd v trim_cap characteristics i trim _ cap trim output current through 1uf capacitor to ground max acceptable board and cap leakage is 50 na 2 100 na all other input and output characteristics vdd = 2.7v 0.8 x vdd_cap v v ih input high voltage (mr#, sda, scl, pwr_on, seq_link, fs#) 3 vdd = 5.0v 0.7 x vdd_cap v vdd = 2.7v 0.2 x vdd_cap v v il input low voltage (mr#, sda, scl, pwr_on, seq_link, fs#) 3 vdd = 5.0v 0.3 x vdd_cap v absolute maximum ratings absolute maximum ratings
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 9 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit internally regulated to 3.6v 0.8 x vdd_cap v v ih input high voltage (mr#, sda, scl, pwr_on, seq_link, fs#) 3 internally regulated to 5.5v 0.7 x vdd_cap v internally regulated to 3.6v 0.2 x vdd_cap v v il input low voltage (mr#, sda, scl, pwr_on, seq_link, fs#) 3 internally regulated to 5.5v 0.3 x vdd_cap v v ol open drain outputs (rst#, fs#, pwr_on, healthy, fault#, pupx, seq_link) i sink = 1ma 0 0.4 v i ol output low current note ? total i sink from all pupx pins should not exceed 3ma or adoc acc specification will be affected 0 1.0 ma v sense positive sense voltage vm pin +0.3 vdd_cap v v monitor monitor threshold step size vm, ain1/ain2 pins 5 mv commercial temp range -3 +3 o c t sa internal temperature sensor accuracy industrial temp range -5 +5 o c t monitor temperature threshold step size internal temp sensor 0.25 o c vref internal 1.25 vref output voltage 1.24 1.25 1.26 v ?40 c to +85 c -0.25 +0.25 % tc internal vref temperature coefficient 0 c to +70 c -0.15 +0.15 % vref acc internal vref accuracy -0.4 +0.4 % ext vref external vref voltage range 0.5 vdd_cap v external vref=1.25v, 0.1%, total pupx i sink < 3ma, v sense ? ? < 3.5v -0.2 0.1 +0.2 % external vref=1.25v, 0.1%, total pupx i sink < 3ma, v sense ? ? ? > 3.5v -0.5 0.3 +0.5 % adoc acc adoc (active dc output control)/margin accuracy internal vref=1.25v, total pupx i sink < 3ma -0.5 0.3 +0.5 % v out_valid minimum output valid voltage vdd_cap voltage at which the pup, rst#, healthy and fault#, fs#, pwr_on seq_link , outputs are valid 1 v vdd_cap rising 2.6 v uvlo uvlo (under voltage lockout) threshold 4 vdd_cap falling 2.5 v note 1 ? range depends on internal regulator set to 3.6v or 5.5v see 12vin specification. note 2 ? see application note 37 which describes the type of capacitors to use to obtain minimum leakage. note 3 ? all logic levels are derived with respect to the volt age present on vdd_cap, when supplied from the vdd input vdd_cap is equal to vdd, under no load. note 4 ? (100mv typ hysteresis)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 10 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) ain1/ain2 adc characteristics symbol parameter notes min typ max unit n resolution 10 bits mc missing codes minimum resolution for which no missing codes are guaranteed 10 bits s/n signal-to-noise ratio conversion rate = 500hz 72 db dnl differential non-linearity -1/2 +1/2 lsb inl integral non-linearity note 1 -1 +1 lsb gain positive full scale gain error note 1 -0.5 +0.5 % offset offset error note 1 -1 +1 lsb adc_tc full scale temperature coefficient 15 ppm/ o c im adc analog adc input impedance 10 m ? ii vref vref input current 250 na ic vref vref input capacitance 200 pf ir vref vref input impedance 1 k ? note 1 - the formula for the total adc inaccuracy is: [((adc read voltage) +/- inl)*(range of gain error)]+range of offset error
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 11 over recommended operating conditions, unless otherwise not ed. all voltages are relative to gnd. see figure 5 and 6 timing diagrams. symbol description conditions min typ max unit t dpon = 0.64ms t dpon = 12.5ms t dpon = 25ms t dpon programmable power-on delay from restart timer expiration to pup x active. t dpon = 50ms -25 t dpon +25 % t dpoff = 0.64ms t dpoff programmable power-off delay from vm x off to pup x inactive t dpoff = 12.5ms -25 t dpoff +25 % t prto = 0.64ms t prto = 25ms t prto = 100ms t prto programmable reset time-out delay t prto = 200ms -25 t prto +25 % t stt = off t stt = 100ms t stt = 200ms t stt programmable sequence termination timer t stt = 400ms -25 t stt +25 % t ftrd fault-triggered restart delay time from restart timer expiration to pup x active after a fault-triggered power- off or force-shutdown. 2.4 s t ftrd acc fault-triggered restart delay accuracy -25 t ftrd +25 % t ctrd command-triggered restart delay time from restart timer expiration to pup x active after command-triggered power-off or force-shutdown. 12.5 ms t ctrd acc command-triggered restart delay accuracy -25 t ctrd +25 % t adc 10-bit adc sampling period time for adc conversion of all 9 channels 2.0 ms t dc_control adoc sampling period update period for adoc of channels a ? d 1.7 ms slow margin, + 10% change in voltage with 0.1% ripple trim_cap=1 f 850 ms t margin margin time from nominal fast margin, + 10% change in voltage with 0.1% ripple trim_cap=1 f 85 ms ac operating charicteristics
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 12 i 2 c-2 wire serial interface ac ope rating characteristics ?100/400 khz over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd. see figure 4 timing diagram. 100khz 400khz symbol description conditions min typ max min typ max units f scl scl clock frequency 0 100 0 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission - note 1 / 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 0.2 0.9 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 0.2 s t r scl and sda rise time note 1 / 1000 1000 ns t f scl and sda fall time note 1 / 300 300 ns t su:dat data in setup time 250 150 ns t hd:dat data in hold time 0 0 ns ti noise filter scl and sda noise suppression 100 100 ns t wr_config write cycle time config configuration registers 10 10 ms t wr_ee write cycle time ee memory array 5 5 ms note: 1 / - guaranteed by design. t r t f t high t low t su:sda t hd:sda t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t w r (for w rite operation only) figure 4 - basic i 2 c serial interface timing timing diagrams
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 13 figure 5 - the SMM764 cascade sequencing the suppli es on and then monitoring for fault conditions. figure 6 - the SMM764 cascade sequencing the supplies off. timing diagrams (continued) t dpona t dponb t dponc t dpond 123 vm a pup a pup b pup c pup d vm b vm c vm d sequence position t dpoffa t dpoffb t dpoffc t dpoffd 321 vm a pup a pup b pup c pup d vm b vm c vm d sequence position
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 14 applications information device operation power supply the SMM764 can be powered by either a 12v input through the 12vin pin or by a 3.3v or 5.0v input through the vdd pin. the 12vin pin feeds an internal programmable regulator t hat internally generates either 5.5v or 3.6v. a voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the vdd input. this voltage arbitration circuit cont inuously checks for these voltages to determine which will power the SMM764. the resultant internal power supply rail is connected to the vdd_cap pin that allows both filtering and hold- up of the internal power supply. to ensure that the input voltage is high enough for reliable operation, an under voltage lockout circuit holds the controlled supplies off until the uvlo thresholds are met. when multiple sequence-link? dev ices are connected, the same vdd and/or 12vin supplies must power all devices. modes of operation the SMM764 has four basic modes of operation (shown in figures 5 through 8): power-on sequencing mode, ongoing operations-monitoring mode, supply margining mode, and power-on sequencing mode. in addition, there are two features: adoc and force-shutdown, which can be used during monitoring and margining mode. a detailed description of each mode and feature follows. active dc output control (adoc tm ) the SMM764 can actively control the dc output voltage of bricks or dc/dc c onverters that have a trim pin during monitoring and margining mode. the converter may be an off-the shelf compact device, or may be a ?roll your own? circuit on the application board. in either case, the SMM764 dramatically improves voltage accuracy (down to 0.2%) by implementing closed-loop adoc active control. this utilizes the dc-dc?s ?trim? pin as shown in figure 12, or an equivalent output voltage feedback adjustment ?vadj?, ?fb?, or ?sense? node in a user?s custom circuit, figure 13. each of the trim x pins on the SMM764 is connected to the trim input pins on the power supply converters. a sense line from the channel?s point-of-load connects to the corresponding vm input. the adoc function cycles through all 4 channels (a-d) every 1.7ms making slight adjustments to the voltage on the associated trim x output pins based on the voltage inputs on the vm x pins. these voltage adjustments allow the SMM764 to control the output voltage of power supply converters to within 0.2% when using a 0.1% external voltage reference. figure 7 - waveform shows four SMM764 channels exhibiting sequence-on to nominal voltage, margin high or low, nominal voltage and then sequence-off ch 1 = 3.3v dc-dc converte r output (yellow trace) ch 2 = 2.5v dc-dc conver ter output (blue trace) ch 3 = 2.0v dc-dc converte r output (purple trace) ch 4 = 1.8v dc-dc converte r output (green trace) figure 8 - waveform shows three SMM764 channels sequencing-on to nominal voltage, margin high and low, and then sequence-off. channel 4 shows the healthy signal. ch 1 = 3.3v dc-dc converte r output (yellow trace) ch 2 = 2.5v dc-dc conver ter output (blue trace) ch 2 = 2.0v dc-dc converter out put (purple trace) ch 4 = healthy signal output (green trace)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 15 a pulse of current either sourced or sunk for 5s every 1.7ms, to the capacitors connected to the trim_cap x pins adjusts the voltage output on the trim x pins. the voltages on the trim_cap x pins are buffered and applied to the trim x pins. the voltage adjustments on the trim x pins cause a slight ripple of less than 1mv on the power supply voltages. the amplitude of this ripple is a function of the trim_cap x capacitor and the trim gain of the converter. application note 37 details the calculation of the trim_cap x capacitor to achieve a desired minimum ripple. each channel can be programmed to either enable or disable the adoc function. when disabled or not active, the trim x pins on the SMM764 are high impedance inputs. if disabled and not used, they can be connected to ground. the voltages on the trim x pins are buffered and applied to the trim_cap x pins charging the capacitors. this allows a smooth transition from the converter powering up to its nominal voltage, to the SMM764 controlling that voltage, and to the adoc nominal setting. the pulse of current can be increased to a 10x pulse of current until the power supply voltages are at their nominal settings by selecting the programmable fast margin option. as the name implies, this option decreases the time required to bring a supply voltage from the converter?s nominal output voltage to the adoc nominal, high, or low voltage setting. power-on cascade sequencing the SMM764 can be programmed to sequence on 32 supplies occupying up to 29 sequence positions. this is accomplished using the seq_link pin. each of the 4 channels (a-d) on a SMM764 has an associated open drain pup output that, when connected to a converter?s enable pin, controls the turn-on of the converter. the channels are assigned sequence positions to determine the order of the sequence. the polarity of each of the pup x outputs is programmable for use with various types of converters. power-on sequencing is initiated on the rising edge of the pwr_on pin. the SMM764 can be programmed to wait until any or all vdd, 12vin, and internal temp (internal temperature) adc readings are within their respective voltage threshold or temperature limits before power- on sequencing is allowed to begin. this ensures that the converters have reached their full supply voltage before they are enabled. on the rising edge of the pwr_on pin the SMM764 will wait a power-on delay time (t dpon ) for any channels in the first sequence position (position 1) and then activate the pup x outputs for those channels. the power-on delay times are individually programmable for each channel. the SMM764 will then wait until all vm x inputs of the channels assigned to the first sequence position are above their user programmable uv1 thresholds, which is called cascade sequencing. at this point, the SMM764 will enter the second sequence position (position 2) and begin to timeout the power-on delay times for the associated channels. this process continues unt il all of the channels assigned to participate in the sequence have turned on and are above their uv1 threshold. once the sequence has completed the status register indicates that all sequenced power supply channels have turned on. after the sequence has completed the SMM764 will begin the adoc of the enabled channels. the power-on sequencing mode ends when the adoc channels are at their nominal voltage setting. the ?ready? bit in the status r egister signifies that the voltages are at their set points. the programmable sequence termination timer can be used to protect against a stalled power-on sequence. this timer resets itself at the beginning of each sequence position. all channels in the sequence position must go above their uv1 threshold before the sequence termination timer times out (t stt ) or the sequence will terminate by pulling the fs# pin low, initiating a force shutdown. the status register contains bits indicating in which sequence position the timer timed out. this sequence termination timer has four settings of off, 100ms, 200ms and 400ms. while the SMM764 is in the power-on sequencing mode the rst# output is held active and the healthy output is held inactive regardless of trigger sources (figure 8). the power-off and force-shutdown trigger options are also disabled while in this mode. furthermore, the SMM764 will not respond to activity on the pwr_on pin or to a power-off i 2 c command during power-on sequencing mode. the SMM764 permits multiple supplies to occupy the same sequence position. when a sequence position is shared, each channel will be enabled after its respective power-on delay. when the last channel occupying a shared sequence position exceeds its uv1 setting the SMM764 will increment to the next applications information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 16 sequence position. any unused channel should be assigned to the null sequence position. ongoing operations-monitoring mode during ongoing operations mode, the part can monitor, and actively control via adoc, and use the force- shutdown operation if necessary. once the power-on sequence is complete, depending on the user programmed settings; the SMM764 will either enter the ongoing oper ations mode directly or wait for adoc to successfully bring all channels within their nominal values. the ongoing operations mode will end when a power-off sequence, or force- shutdown has been initiated. once the ongoing operations mode has begun, the SMM764 continues to monitor all vm x inputs, the vdd and 12vin inputs, and two temperature sensor inputs with a 10-bit adc. each of these inputs is sampled and converted by the adc every 2ms. the adc input has a range of 0v to four times the voltage on vref for inputs vm a-d and the vdd input. the range is extended to 12 times vref for the 12vin input and is reduced to two times vref for the ain1 and ain2 inputs. the SMM764 monitors internal temperature using the 10-bit adc and the automonitor function. two under- temperature and two over-temperature thresholds can be set, each with its own programmable threshold options and consecutive conversion, before trigger counter. resolution is 0.25 c per bit scaled over the range of -128 c to 127.75 c. the temperature value can be acquired over the i 2 c bus as a 10-bit signed two's complement value. the SMM764 compares each resulting adc conversion with two programmable 10-bit under- voltage limits (uv1, uv2) and two programmable 10- bit over-voltage limits (ov1, ov2) for the corresponding input. a consecutive conversion counter is used to provide filtering of the adc inputs. each limit can be programmed to require 1, 2, 4 or 6 consecutive out-of-limit conversions before it is said to be in fault. one in-limit conversion will remove the fault from the threshold limit. this provides digital filtering of the monitored inputs. the adc inputs vm a-d can use additional filtering by connecting a capacitor from the corresponding cap x pins to ground to form an analog rc filter (r=25k ? ). the input is considered to be in a fault condition if any of its limit thresholds are in fault. setting an ov threshold limit to full-scale (3ff hex ), or setting a uv threshold limit to 000 hex , ensures that the limit can never be in fault. the status registers provide the real-tim e status of all monitored inputs. the voltage threshold limits for inputs vm a-d , vdd and 12vin can be programmed to trigger the rst# and healthy outputs as well as a fault-triggered force- shutdown and power-off operation when exceeded. the threshold limits for the internal temperature sensor and the ain1 and ain2 inputs can be programmed to assert the rst#, healthy, and fault# output pins the healthy and fault# outputs of the SMM764 are active as long as the monitored threshold remains in violation. the rst# output also remains active as long as the monitored threshold remains in violation. however, once the threshold violation goes away, the rst# will remain active for a programmable reset timeout period (t prto ). the SMM764 treats command-triggered force- shutdown and power-off operations, those caused by i 2 c commands and assertion of the fs# and pwr_on pin, differently than those caused by a fault-triggered forced-shutdown and power-off conditions, those caused by uv/ov violations or a sequence termination timer expiration. the mode in which either a forced-shut down or a power-off occurs effects how or whether the SMM764 will restart, and the number of allowable retries permitted. temperature sensor accuracy the internal temperature sensor accuracy is 5 o c from -40 to +85 o c. the sensor measures the temperature of the SMM764 die and the ambient temperature. if vdd is at 5v, the die temperature is +2 o c and at 12v, it is +4 o c. in order to calculate this difference in specific applications, measure the vdd or 12vin supply current and calculate the power dissipated and multiply by 80 o c/w. for instance, 5v and 5ma is 25mw, which creates a 2 o c offset. margining the SMM764 has two additional adoc voltage settings for channels a-d, margin high and margin low. the margin high and margin low voltage settings can range from 0.3v to vdd of the converters? nominal output voltage, depending on the specified margin range of the dc-dc converter. these settings are stored in the configuration registers and are loaded into the adoc voltage setting by margin commands issued via the i 2 c bus. the channel must be enabled for adoc in order to enable margining. the margin command registers contain two bits for applications information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 17 applications information (continued) each channel that decode the commands to margin high, margin low, or control to the nominal setting. therefore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. once the SMM764 receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. when all channels are at their voltage setting, a bit is set in the margin status registers. note: configuration writes or reads of registers 00 hex to 0f hex should not be performed while the SMM764 is margining. power-off cascade sequencing the SMM764 performs power-off sequencing in the reverse order of power-on sequencing. power-off cascade sequencing can be initiated by the pwr_on pin, via i 2 c control or triggered by a fault condition on any of the monitored inputs. toggling the pwr_on pin low will initiate the power-off sequence. to enable software control of the power-off sequencing feature, the SMM764 offers an i 2 c command to initiate power-off sequencing while the pwr_on pin is asserted. furthermore, power-off sequencing can be initiated by a fault condition on a monitored input. once power-off sequencing begins, the SMM764 will wait a power-off delay time (t dpoff ) for any channel in the last sequence position and then deactivate the pup outputs for those channels. the power-off delay times are individually programmable for each channel. the SMM764 will then wait until all vm x inputs of the channels assigned to that sequence position are below the programmed off thresholds. at this point, the SMM764 will move to the next sequence position and begin to timeout the power-off delay times for the associated channels. this process continues until all of the channels in the sequence have turned off and are below their off thresholds. the status register rev eals that all sequenced channels have turned off. the power-off sequencing mode ends when all sequenced supplies are below their off thresholds. the programmable sequence termination timer can be used to protect against a stalled power-off sequence. this timer resets itself at the beginning of each sequence position. all channels in the sequence position must go below their off threshold before the sequence termination timer times out (t stt ) or the sequence will terminate and all pup outputs will be switched to their inactive state. this timer has four settings of off: 100ms, 200ms and 400ms. the sequence termination timer can be disabled separately for power-off sequencing. while the SMM764 is in the power-off sequencing mode, the rst# output is held active and the healthy output is held inactive, regardless of trigger sources (figure 8). the force-shutdown trigger option is also disabled while in this mode. furthermore, the SMM764 will not respond to activity on the pwr_on pin during power-off sequencing mode. force shutdown the force-shutdown operation brings all pup x outputs to their inactive state. this operation is used for an emergency shutdown when there is not enough time to sequence the supplies off. the force-shutdown operation shuts off all sequenced channels pulls the pwr_on pin low, and waits for the supply voltages to drop below their respective off thresholds before beginning a restart sequence. a force-shutdown operation can be initiated by any one of four events. the first two methods for initiating a force-shutdown are always enabled. simply taking the fs# pin low will initiate a force-shutdown operation and maintain it until the pin is brought high again. an i 2 c force-shutdown command allows the force- shutdown operation to be in itiated via software control. this bit is cleared after all sequenced channels have dropped below their off voltage threshold.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 18 applications information ( continued ) linked operation the SMM764 can be linked to multiple sequence- link ? devices to create a seamless multi-channel power manager. with linked operation 8 sequence- link devices in a system can sequence up to 46 supplies within 29 sequence positions. the sequencing in this mode can be interlaced, sequencing a supply from device a, then from device b, then again from device a, etc. this extended sequencing is made possible by the inclusion of a seq_link pin. for this mode of operation, the control pins, including seq_link, pwr_on, and fs# on each device must be tied together. in addition, the vdd and 12v supply must also be connected on all linked devices. as a consequence when multiple devices are linked together, all devices must be powered by the same supply. restart there are two possible condi tions in which a restart sequence may be initiated. the first instance occurs when either the fs# pin is asserted or the pwr_on pin is pulled low thus initiating a command-triggered restart. the second condition occurs when a user programmable fault triggers a force-shutdown operation or a power-off seque nce thus resulting in a fault-triggered restart. in either case, the SMM764 w ill wait until all voltages have fallen below their user programmable off thresholds, after all channels are off, the pwr_on pin will continue to be held low for a period of time dependent on the nature of the fault. when a power-off or force-shutdown condition results from a command-triggered power-off or force- shutdown, the SMM764 will automatically begin the restart procedure. when restart begins an internal timer will begin to timeout for a command-triggered restart delay (t ctrd ) of 12.5 ms. after this time has expired the pwr_on pin is released, allowing the power-on sequence to begin. when a power-off or force-shutdown condition results from a fault-triggered power-off or force-shutdown, the SMM764 may or may not begin the restart procedure (see programmable retri es), if restart begins the internal timer will begin to timeout a fault-triggered restart delay (t ftrd ) of 2.4 s before the pwr_on pin is released allowing the power-on sequence to begin. if the SMM764 is programmed to wait for vdd, 12vin, or internal temp to be valid (above uv1 and below ov1) before power-on sequencing may commence, then this condition will be checked after the restart timer has expired and the pwr_on pin has been released. the conditions that may lead to a fault-triggered restart include any channel exceeding its user programmable thresholds (ov or uv), set to trigger either a force-shutdown or a power-off sequence. in addition, in the event that the sequence termination timer times out before a channel reaches its uv1 or off threshold, during sequencing, a fault-triggered restart occur. i 2 c power off control power-on sequencing is only permitted while the pwr_on pin is active. once the pwr_on pin is active and the SMM764 has entered monitoring mode, an i 2 c command may be issued to commence the power-off sequence. this condition will continue until an i 2 c ?power on? command is issued. programmable retries in the event of a persisten t system fault, the SMM764 may be programmed to limit the number of fault- triggered restarts it will allow. this programmable setting ensures that the SMM764 will not enter a hiccup-mode of operation, while still reducing susceptibility to transient fault conditions. in the event of a fault-tri ggered restart the fault will be registered and internally compared to the maximum number of allowable faults. if this number is exceeded then the fault condition will be latched and the pwr_on and fs# pins will be pulled low while the rst# output is asserted. this fault condition will remain latched until power is cycled on the SMM764, at which point the pwr_on and fs# pins will be released, the number of faul ts will be reset zero, and the restart sequence will begin. the allowable programmable setting include one, three, and unlimited retries.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 19 applications information ( continued ) undervoltage lockout the internally filtered supply voltage as seen across vdd_cap is edge-triggered to lock out false or nuisance signals during both the power-on and power- off sequences. if the vdd_cap voltage falls below 2.5v (figure 10), an internal undervoltage lockout (uvlo) circuit will reset all internal logic. once power has recovered above 2.6v the SMM764 will restart as if a command-triggered power-off had been issued. vdd_cap 2.5v 3.6v, 5.5v uvlo (internal) 2.6v figure 10 - timing sequence recovering from a vdd_cap power ?brown-out?
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 20 vdd_cap 1 1 2 2 3 3 j1 3 jumper 3.3vout 2.5vout to additional converters sw1 sw pushbutton fault# healthy reset# c68 0.01uf +12vin place trim caps as close to device as possible +5vin mr# vdd_cap c41 0.01uf 1 2 d15 diode c43 0.01uf place trim caps as close to device as possible c44 0.1uf vdd c45 0.022uf 1 1 2 2 3 3 j2 3 jumper ref 1 gnd 2 en 3 vin 4 vout 5 u10 lm4121 +vout 1 +vout 2 sense 3 +vout 4 gnd 5 gnd 6 +vin 7 +vin 8 pwr en 9 trim 10 enable 11 u13 tyco axh010a0f c12 0.01uf c13 0.1uf 0 c14 0.01uf c15 0.1uf c42 0.01uf sda r8 10k r9 10k vdd d14 healthy r10 10k d3 rst d4 fault 1 1 2 2 3 3 j3 3 jumper +vout 1 +vout 2 sense 3 +vout 4 gnd 5 gnd 6 +vin 7 +vin 8 pwr en 9 trim 10 enable 11 u14 tyco axh010a0f c16 0.01uf c17 0.1uf c18 0.01uf c24 1uf c19 0.1uf c25 0.01uf sw2 sw pushbutton 1 1 2 2 3 3 j4 3 jumper +vout 1 +vout 2 sense 3 +vout 4 gnd 5 gnd 6 +vin 7 +vin 8 pwr en 9 trim 10 enable 11 u15 tyco axh010a0f c20 0.01uf c21 0.1uf c1 0.1uf c22 0.01uf c23 0.1uf sda 1 scl 2 a2 3 mr# 4 pwr_on/off 5 fs# 6 fault# 7 healthy 8 rst# 9 ain1 10 ain2 11 gnd 12 seq_link 13 vref 14 filt_cap 15 vmd 26 capd 27 pupd 28 trimd 29 trim_capd 30 vmc 31 capc 32 pupc 33 trimc 34 trim_capc 35 vmb 36 capb 37 pupb 38 trimb 39 trim_capb 40 vma 41 capa 42 pupa 43 trima 44 trim_capa 45 vdd 46 12vin 47 vdd_cap 48 gnd 19 gnd 24 u1 SMM764 c46 0.1uf c32 0.1uf c33 0.01uf c34 0.01uf c35 0.01uf c36 0.1uf + c37 10uf c38 0.1uf vdd 1 2 r11 47k 1 2 r12 47k 1 2 r13 47k 1 2 r16 47k t rt1 10k r14 30k gnd 1 scl 2 gnd3 3 sda 4 rsrv5 5 mr 6 +10v 7 rsrv8 8 +5v 9 rsrv10 10 j7 i2c r15 30k c67 0.01uf t rt2 10k vdd c66 0.01uf j5 vref a2 +vout 1 +vout 2 sense 3 +vout 4 gnd 5 gnd 6 +vin 7 +vin 8 pwr en 9 trim 10 enable 11 u12 tyco axh010a0f c39 0.01uf 1 2 r1 47k scl 1.5vout 1.2vout 1 2 r2 47k c2 0.01uf c3 0.01uf c4 0.01uf c5 0.1uf c6 0.01uf c47 0.01uf c48 0.1uf c49 0.022uf + c7 10uf ref 1 gnd 2 en 3 vin 4 vout 5 u11 lm4121 1 1 2 2 3 3 j6 vref_in pwr_on c8 0.1uf c50 0.1uf 1 2 r3 47k j8 vref 1 1 2 2 3 3 j9 vref_in vdd_cap vdd 1 2 r4 47k sda 1 scl 2 a2 3 mr# 4 pwr_on/off 5 fs# 6 fault# 7 healthy 8 rst# 9 ain1 10 ain2 11 gnd 12 seq_link 13 vref 14 filt_cap 15 vmd 26 capd 27 pupd 28 trimd 29 trim_capd 30 vmc 31 capc 32 pupc 33 trimc 34 trim_capc 35 vmb 36 capb 37 pupb 38 trimb 39 trim_capb 40 vma 41 capa 42 pupa 43 trima 44 trim_capa 45 vdd 46 12vin 47 vdd_cap 48 gnd 19 gnd 24 u2 SMM764 c9 0.1uf c26 1uf c27 .01uf smx3200 programmer connector fs# c28 1uf c29 .01uf fault# healthy optional external temperature sensors link vdd r17 10k r18 10k reset# a2 mr# r5 10k r6 10k vdd d13 healthy r7 10k d2 rst# d1 fault# c10 0.01uf vdd c11 0.1uf c40 0.01uf r19 10k vdd r21 10k r20 10k vdd_cap c30 1uf c31 0.01uf input voltage option either +5v or +12v figure 11 ? SMM764 distributed power applications schematic. the accuracy of the external reference (u10) sets the accuracy of the adoc function. total accuracy with a 0.1% external reference is 0.2% applications information ( continued )
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 21 development hardware & software the end user can obtain the summit smx3200 programming system for device prototype development. the smx3200 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the smx3200 programming dongle/cable interfaces directly between a pc?s parallel port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the SMM764 via the programming dongle and cable. an example of the connection interface is shown in figure 15. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper device operation in the end application. pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector. 9 7 5 3 1 10 8 6 4 2 SMM764 sda scl vdd_cap gnd 0.1 f mr# d1 1n4148 figure 12 ? smx3200 programmer i 2 c serial bus connections to program the SMM764. note that the mr# pin does not need to be connected to pin 6 for programming purposes. the latest revisions of all software and an application brie f describing the smx3200 is avai lable from the website at: http://www.summitmicro.com/tech _support/program_kit/smx3200.htm
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 22 serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating start and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 4-bit device type identifier sa[3:0] (slave address) and a 3-bit bus address ba[2:0]. the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the SMM764. the device type identifier for the memory array is generally set to 1010 bin following the industry standard for a typical nonvolatile memory. there is an option to change the identifier to 1011 bin allowing it to be used on a bus that may be occupied by other memory devices. the configuration registers are grouped with the memory array and thus use 1010 bin or 1011 bin as the device type identifier. the command and status registers as well as the 10-bit adc are accessible with the separate device type identifier of 1001 bin . the bus address bits ba[1:0] are programmed into the configuration registers. bu s address bit ba[2] can be programmed as either 0 or biased by the a2 pin. the bus address accessed in the address byte of the serial data stream must match the setting in the SMM764 and on the a2 pin. any access to the SMM764 on the i 2 c bus will temporarily halt the monitoring function. this does not affect the adoc function, which will continue functioning and control the dc outputs. this is true not only during the monitor mode, but also during power-on and power-off sequencing when the device is monitoring the channels to determine if they have turned on or turned off. the SMM764 halts the monitor function from when it acknowledges the address byte until a valid stop is received. write writing to the memory or a configuration register is illustrated in figures 13, 14, 15, 17 and 19. a start condition followed by the address byte is provided by the host; the SMM764 responds with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM764 responds with an acknowledge; the host then clocks in on byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the configuration registers, memory, command and status registers and adc registers must be set before data can be read from the SMM764. this is accomplished by a issuing a dummy write command, which is simply a write command that is not followed by a stop condition. the dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the de sired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 16, 18 and 21 for an illustration of the read sequence. i 2 c programming information
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 23 write protection the SMM764 powers up into a write protected mode. writing a code to the volatile write protection register can disable the write protection. the write protection register is located at address 87 hex of slave address 1001 bin . writing 0101 bin to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101 bin to bits [3:0] allow writes to the configuration registers. the write protection can re- enable by writing other codes (not 0101 bin ) to the write protection register. writing to the write protection register is shown in figure 13. configuration registers the majority of the configuration registers are grouped with the general-purpose memory located at either slave address 1010 bin or 1011 bin . bus address bits ba[2:1] are programmable. the bus address bit ba[0], however, is used to differ entiate the general-purpose memory from the configurat ion registers and should be set to 1 bin when accessing the configuration registers . bus address bit ba[2] can be programmed as a ?virtual 0? or biased by the a2 pin. an additional configuration register is located at address 84 hex of slave address 1001 bin . writing and reading the configuration registers is shown in figures 14, 15, 16, 17, and 18 note: configuration writes or reads of registers 00 hex to 0f hex should not be performed while the SMM764 is margining. general-purpose memory the 2k-bit general-purpose memory is located at either slave address 1010 bin or 1011 bin . bus address bits ba[2:1] are programmable. the bus address bit ba[0], however, is used to differentiate the general- purpose memory from the configuration registers and should be set to 0 bin when accessing general purpose memory . bus address bit ba[2] can be programmed as a ?virtual 0? or biased by the a2 pin. the slave address and bus address must be set each time the memory is accessed. memory writes and reads are shown in figures 19, 20 and 21. command and status registers the command and status registers are located at slave address 1001 bin . writes and reads of the command and status registers are shown in figures 22 and 23. adc conversions an adc conversion on any monitored channel can be performed and read over the i 2 c bus using the adc read command. the adc read command, shown in figure 24, starts with a dummy write to the 1001 bin slave address. bits [6:3] of the word address byte are used to address the desired monitored input. once the device acknowledges the channel address, it begins the adc conversion of the addressed input. this conversion requires 70 s to complete. during this conversion time, acknowledge polling can be used. the SMM764 will not acknowledge the address bytes until the conversion is complete. when the conversion has completed, the SMM764 will acknowledge the address byte and return the 10-bit conversion along with a 4-bit channel address echo. graphical user interface (gui) device configuration utilizing the windows based SMM764 graphical user interface (gui) is highly recommended. the software is available from the summit website (website at: ( http://www.summitmicro.c om/tech_support/tech.htm# gui . using the gui in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the SMM764. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. slave address bus address register type 1001 bin ba2 ba1 ba0 write protection register, command and status registers, one configuration registers, adc conversion readout ba2 ba1 0 2-k bits of general-purpose memory 1010 bin or 1011 bin ba2 ba1 1 configuration registers table 1 - address bytes used by the SMM764. i 2 c programming information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 24 s t a r t w a c k master slave a c k configuration register address = 87 hex 1 0000111 0 1010101 s t o p data = 55 hex a c k 1 0 0 1 b a 2 bus address b a 1 b a 0 5 hex unlocks general purpose ee 5 hex unlocks configuration registers write protection register address 8 hex 7 hex figure 13 ? write protection register write s t a r t 1 b a 2 bus address w a c k master slave a c k 1 b a 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k figure14 ? configuration register byte write d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master slave data (16) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k s t a r t 1 bus address w a c k master slave a c k 1 b a 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data a c k b a 1 figure 15 ? configuration register page write i 2 c programming information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 25 s t a r t 1 b a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 1 b a 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k b a 2 bus address 1 s a 0 0 1 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) b a 1 figure 16 - configuration register read s t a r t w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 b a 2 bus address b a 1 b a 0 figure 17 - configuration register with slave address 1001 bin write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 b a 2 bus address b a 1 b a 0 1 0 0 1 b a 2 bus address b a 1 b a 0 figure 18 - configuration register with slave address 1001 bin read i 2 c programming information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 26 s t a r t 1 bus address w a c k master slave a c k 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k b a 2 0 b a 1 figure 19 ? general purpose memory byte write bus address b a 2 0 s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k b a 1 figure 20 - general purpose memory page write s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k 1 s a 0 0 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address b a 2 0 bus address b a 1 b a 2 0 b a 1 figure 21 - general purpose memory read i 2 c programming information (continued)
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 27 s t a r t w a c k master slave a c k command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 b a 2 bus address b a 1 b a 0 figure 22 ? command and status register write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 b a 2 bus address b a 1 b a 0 1 0 0 1 b a 2 bus address b a 1 b a 0 figure 23 - command and status register read s t a r t 1 0 0 1 b a 2 bus address b a 1 b a 0 w c h 3 c h 2 c h 1 c h 0 a c k s t a r t 1 0 0 1 b a 2 bus address b a 1 b a 0 r s t a r t 1 0 0 1 b a 2 bus address b a 1 b a 0 r c h 3 c h 2 c h 1 c h 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k n a c k master master slave slave channel address echo channel address 0 0 0 0 a c k 10-bit adc data a c k a c k 0 0 i 2 c programming information (continued) figure 24 ? adc conversion read
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 28 default configuration register settings ? SMM764fc-285 register contents register contents register contents r0 fd r82 82 rba 02 r1 84 r83 66 rbb 23 r2 0e r84 2a rbc 03 r3 00 r85 cd rbd e0 r4 0e r86 12 rbe 03 r5 80 r87 e1 rbf e0 r6 0e r88 49 rc0 03 r7 c7 r89 d7 rc1 38 rc ff r8a 81 rc2 03 rd 00 r8b c3 rc3 38 re 05 r8c 2a rc4 01 rf 08 r8d 29 rc5 90 r10 7f r8e 12 rc6 01 r11 7f r8f 3d rc7 90 r12 7f r90 49 rc8 00 r13 7f r91 85 rc9 00 r30 fd r92 81 rca 00 r31 6e r93 71 rcb 00 r32 0e r94 29 rcc 03 r33 da r95 d7 rcd ff r34 0e r96 11 rce 03 r35 46 r97 ec rcf ff r36 0e r98 49 rd0 00 r37 80 r99 48 rd1 00 r3c 00 r9a 81 rd2 00 r3d 12 r9b 33 rd3 00 r3e 50 r9c 29 rd4 03 r40 fd r9d 9a rd5 d8 r41 9d r9e 11 rd6 03 r42 8e r9f ae rd7 d8 r43 2d rb0 02 re0 00 r44 0e rb1 67 re0 00 r45 a2 rb2 02 re1 3d r46 0f rb3 52 re2 00 r47 20 rb4 03 re3 3d r4c 00 rb5 ff re4 00 r4d 12 rb6 03 re5 3d r4e 50 rb7 ff re6 00 r80 4a rb8 02 re7 3d r81 7b rb9 23 rc1 the default device ordering number is SMM764fc-285. it is programmed with the register contents as shown above and tested over the commercial temperature range with a vref setting of 1.25v. other standard external vref voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300. the value is derived from the customer supplied hex f ile. new device suffix numbers are assigned to non-default requirements. if other vref values are required, please contact a summit microelectronics sales representative.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 29 package a b pin 1 indicator inches (millimeters) 0.002 - 0.006 (0.05-0.15) max. 0.047 (1.2) 0.037 - 0.041 0.95 - 1.05 0.018 - 0.030 (0.45 - 0.75) 0.039 (1.00) 0.02 (0.5) bsc 0.007 - 0.011 (0.17 - 0.27) detail "a" detail "b" (b) (a) (a) 0.354 (9.00) bsc 0.276 (7.00) bsc (b) 48 pin tqfp package 0 o min to 7 o max ref jedec ms-026 ref
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 30 part marking ordering information summit SMM764f ayyww pin 1 annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) SMM764 f package f=48 lead tqfp summit part number specific requirements are contained in the suffix such as hex code, hex code revision, etc. the calibrated vref voltage settings are standard values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300 nnn part number suffix (see page 28) c temp range c=commercial blank=industrial
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 31 terms and definitions fault-triggered this term refers to either a power -off or force-shutdown operation. when a uv, ov, or sequence termination condition trigger a power-off or force-shutdown a fault triggered power- off or force-shutdown is said to occur. this sets the restart delay at 2.4s, and can limit the number of allowable retries. this term has no correlation to the fault pin. command-triggered this term refers to either a power-off or force-shutdown operatio n. when either the fs# or pwr_on pin is asserted or an i 2 c command is issued a command-triggered power-off or force-shutdown is said to occur. this sets the restart delay at 12.5ms, and will not limit the number of allowable retries. adoc? adoc (active dc output control) is a proprietary secondary closed loop compensation control, used to maintain output voltages to 0.2%. power-off power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. cascaded power-off sequencing refers to a feed back based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable off threshold before the next sequence position is allowed to turn off. channels in the same sequence positi on are not capable of cascaded power-off sequencing. power-on power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. cascaded power-off sequencing refers to a feedback based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable off threshold before the next sequence position is allowed to turn off. channels in the same sequence positi on are not capable of cascaded power-off sequencing. force-shutdown when all supplies are immediately disabled without regard to sequence position, or any other quantity. sequence-link? when more than one SMM764 or smm766 derivatives are connected creating a seamless multi-channel network. uv programmed under voltage threshol d for monitored channels and supplies ov programmed over voltage threshol d for monitored channels and supplies uvlo undervoltage lockout. prevents voltage at vdd or 12vin pin from powering the SMM764 until proper operating voltages have been reached. margin the ability to change the nominal output voltage by use of trim pin. adc analog to digital converter. converts an alog voltage to digital voltage. SMM764 represents all measured voltages by 10-bit digital reading. retries the number of times the SMM764 will restar t after a fault-triggered power-off or force- shutdown. restart when the SMM764 begins power on seq uencing, includes initial power-on sequence. power-on delay delay from restart timer expiration to pup y pin active power-off delay programmable delay from vm x off to pup y inactive sequence termination when a supply fails to reach its programmed uv, or off, threshold before expiration of internal timer. monitoring when any quantity including temperature, and voltage is converted to a digital value by the adc and compared against a user programmable setting. gui graphical user interface. program that reads from and writes to non-volatile registers on the SMM764 and displays results in accordance to register function.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 32 notice note 1 - this is a preliminary information data sheet that describes a summit product current ly in pre-production with limited characterization. revision 1.1 - this document supersedes all previous versions. data sheet updates c an be accessed by ?right? or ?left? mouse c licking on the link: http://www.summitmicro.com/prod_select/summary/SMM764.htm device errata sheets can be accessed by ?right? or ?left? mouse clicking on the link: http://www.summitmicro.com/errata/SMM764 summit microelectronics, inc. reserves the ri ght to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. summit microelec tronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the inform ation in this publication has been carefully checked, summi t microelectronics, inc. shall not be liabl e for any damages arising as a result o f any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless su mmit microelectronics, inc. receiv es written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2005 summit microelectronics, inc. programmable analog for a digital world? adoc tm and sequence-link tm are registered trademarks of summit microelectronics inc., i 2 c is a trademark of philips corporation.
SMM764 preliminary information summit microelectronics, inc 2098 1.1 6/29/2005 33 document rev. description date owner 1.0 preliminary datasheet jj 1.1 vih & vil modified for 0.8 vih and 0.2 vil logic levels. trim cap description changed to be left floating when unused. 6/29/2005 jj

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